MERASA is a European Union Framework 7 research project, investigating the design of systems for worst case execution time analysis.
The MERASA project will develop multi-core processor designs (from 2 to 16 cores) for hard real-time embedded systems hand in hand with timing analysis techniques and tools to guarantee the analysability and predictability regarding timing of every single feature provided by the processor. Design exploration activities will be performed in conjunction with the timing analysis tools.
The project will address both static WCET analysis tools (the OTAWA toolset) as well as hybrid measurement-based tools (RapiTime) and their interoperability. It will also develop system-level software with predictable timing performance. Visit MERASA for more details and see IEEE Micro September/October 2010 (vol. 30 no. 5)