Rapita CEO contributes to award winning paper at ISCA 2009

The HiPEAC Paper Award has been awarded to a paper entitled "Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems" at the International Symposium on Computer Architecture (ISCA 09). The paper was co-authored by Marco Paolieri, Eduardo Quiñones, Francisco Cazorla (all from the Barcelona Supercomputing Center), Guillem Bernat (CEO of Rapita Systems) and Mateo Valero (of Universitat Politècnica de Catalunya and Barcelona Supercomputing Center). The paper proposes a multicore architecture with shared resources that allows the execution of applications with hard real-time. The architecture supports the analysis of the hard real-time tasks to see if they can meet their deadlines, even in the presence of inter-thread interference. This paper is available for download, below. HiPEAC is the European Network of Excellence on High Performance and Embedded Architecture and Compilation. Its mission is to:

• Steer and increase the European research in the area of high-performance and embedded computing systems
• stimulate cooperation between academia and industry
• stimulate cooperation between computer architects and tool builders

Further information on HiPEAC can be found at http://www.hipeac.net