Your browser does not support JavaScript! Skip to main content
Free 30-day trial DO-178C Handbook RapiCoupling Preview DO-178C Multicore Training Multicore Resources
Rapita Systems
 

Industry leading verification tools

Rapita Verification Suite (RVS)

RapiTest - Functional testing for critical software RapiCover - Low-overhead coverage analysis for critical software RapiTime - In-depth execution time analysis for critical software RapiTask - RTOS scheduling visualization RapiCoverZero - Zero-footprint coverage analysis RapitimeZero - Zero-footprint timing analysis RapiTaskZero - Zero-footprint event-level scheduling analysis RVS Qualification Kits - Tool qualification for DO-178 B/C and ISO 26262 projects RapiCouplingPreview - DCCC analysis

Multicore Verification

MACH178 - Multicore Avionics Certification for High-integrity DO-178C projects MACH178 Foundations - Lay the groundwork for A(M)C 20-193 compliance Multicore Timing Solution - Solving the challenges of multicore timing analysis RapiDaemon - Analyze interference in multicore systems

Other

RTBx - The ultimate data logging solution Sim68020 - Simulation for the Motorola 68020 microprocessor

RVS Software Policy

Software licensing Product life cycle policy RVS Assurance issue policy RVS development roadmap

Industry leading verification services

Engineering Services

V&V Services Data Coupling & Control Coupling Object code verification Qualification Training Consultancy Tool Integration Support

Latest from Rapita HQ

Latest news

Rapita partners with Asterios Technologies to deliver solutions in multicore certification
SAIF Autonomy to use RVS to verify their groundbreaking AI platform
RVS 3.22 Launched
Hybrid electric pioneers, Ascendance, join Rapita Systems Trailblazer Partnership Program
View News

Latest from the Rapita blog

How emulation can reduce avionics verification costs: Sim68020
Multicore timing analysis: to instrument or not to instrument
How to certify multicore processors - what is everyone asking?
Data Coupling Basics in DO-178C
View Blog

Latest discovery pages

Military Drone Certifying Unmanned Aircraft Systems
control_tower DO-278A Guidance: Introduction to RTCA DO-278 approval
Picture of a car ISO 26262
DCCC Image Data Coupling & Control Coupling
View Discovery pages

Upcoming events

IEEE SMC-IT/SCC 2025
2025-07-28
DASC 2025
2025-09-14
DO-178C Multicore In-person Training (Fort Worth, TX)
2025-10-01
DO-178C Multicore In-person Training (Toulouse)
2025-11-04
View Events

Technical resources for industry professionals

Latest White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP
Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook
Efficient Verification Through the DO-178C Life Cycle
View White papers

Latest Videos

How to make AI safe in autonomous systems with SAIF
Rapita Systems - Safety Through Quality
Simulation for the Motorola 68020 microprocessor with Sim68020
AI-driven Requirements Traceability for Faster Testing and Certification
View Videos

Latest Case studies

GMV case study front cover
GMV verify ISO26262 automotive software with RVS
Kappa: Verifying Airborne Video Systems for Air-to-Air Refueling using RVS
Supporting DanLaw with unit testing and code coverage analysis for automotive software
View Case studies

Other Resources

 Webinars

 Brochures

 Product briefs

 Technical notes

 Research projects

 Multicore resources

Discover Rapita

Who we are

The company menu

  • About us
  • Customers
  • Distributors
  • Locations
  • Partners
  • Research projects
  • Contact us
  • Careers
  • Working at Rapita

Industries

  Civil Aviation (DO-178C)   Automotive (ISO 26262)   Military & Defense   Space

US office

+1 248-957-9801
info@rapitasystems.com Rapita Systems, Inc., 41131 Vincenti Ct., Novi, MI 48375, USA

UK office

+44 (0)1904 413945
info@rapitasystems.com Rapita Systems Ltd., Atlas House, Osbaldwick Link Road, York, YO10 3JB, UK

Spain office

+34 93 351 02 05
info@rapitasystems.com Rapita Systems S.L., Parc UPC, Edificio K2M, c/ Jordi Girona, 1-3, Barcelona 08034, Spain
Back to Top Contact Us

PROARTIS: thoughts on Statistics, Randomness and Timing

Ian Broster
2012-04-24

We're involved in an exciting research project at the moment, called PROARTIS, that's taking a very unusual approach to timing analysis. So I thought that it would be worth writing about here. The research in PROARTIS is starting to take shape now and we're thinking about how we can use the technology in RVS/RapiTime.

The basis of the project goes a bit like this.

Statistics

Lots of people use probabilities to be able to reason about software, but in the context of worst case execution time (WCET) analysis it gets a bit tricky. One approach to estimating the worst case execution time is to take many end-to-end timing measurements of the system, fit them to a distribution (like a normal distribution) and then make some prediction about the tail of the distribution.

However, there is a fundamental problem with this approach in that most of the maths that you would apply to do this relies on the assumption that the measurements you take are from a "random" source - effectively that your measurements are i.i.d (taken from independent and identically distributed random variables). Unfortunately we know that computers don't really behave randomly - indeed their deterministic nature seems to go completely against the idea that execution times exhibit variations that are appropriate for statistical analysis.

Nevertheless, if we could treat the measurements as coming from a random i.i.d. source, then a whole bunch of mathematics/statistics would suddenly become available to make sense of your timings.

Random

So what PROARTIS does is to effectively make the timing behaviour of the hardware random, not deterministic. To actually put random number generators in the hardware to affect the way that it works. This does not change the functional behaviour of the software, but it does change the speed/timing. For example, one key way to do this is to have a randomized cache-replacement policy instead of e.g. LRU (least recently used). The effect of this is that you never know in advance whether a memory access is a cache hit or a cache miss.

Yet, what you do know is the probability of a cache hit or a cache miss! And you know that your measurements are a bit closer to i.i.d. So now, if you have enough measurements, then you can justifiably use some statistics to predict the worst case software behaviour. The statistics can include extreme value theory, which in turn can be used to study the tail of the distribution.

Timing

Ultimately, with randomized hardware, instead of a single value bound (WCET ≤ x) we can achieve a distribution of values (WCET ≤ f(x) for some probability p). In other words, instead of a single worst case execution time (which perhaps has to consider many more cache misses than you would like it to), we can say with a quantifiable and very high probability that the execution of the software will not exceed a particular time.

This has a really useful side-effect: time composability. That is, that making the timing behaviour more randomized (non-deterministic), you decouple some of the future timing behaviour of the system from the execution state (i.e. what's happened in the past). This means that it gets much easier to reason about how the different parts of the system interact when you plug them together.

I look forward to seeing how this develops. Please see http://www.proartis-project.eu/ for papers and other information.

PROARTIS is a project funded from the European Community's Seventh Framework Programme (FP7/2007-2013) under grant agreement n° 249100, PROARTIS.

DO-178C webinars

DO178C webinars

White papers

Mitigation of interference in multicore processors for A(M)C 20-193
Sysgo WP Developing DO-178C and ED-12C-certifiable multicore software
DO178C Handbook Efficient Verification Through the DO-178C Life Cycle
A Commercial Solution for Safety-Critical Multicore Timing Analysis

Related blog posts

Hardware acceleration features that make real-time hard – pipelined architectures

.
2012-11-28

DO-178B, DO-178C and Worst-Case Execution Time

.
2012-11-19

Hardware acceleration features that make real-time hard – an overview

.
2012-10-29

Goldilocks WCET: Not too optimistic, not too pessimistic

.
2012-10-08

Pagination

  • First page « First
  • Previous page ‹ Previous
  • Page 1
  • Page 2
  • Current page 3
  • Page 4
  • Page 5
  • Page 6
  • Next page Next ›
  • Last page Last »
  • Solutions
    • Rapita Verification Suite
    • RapiTest
    • RapiCover
    • RapiTime
    • RapiTask
    • MACH178

    • Verification and Validation Services
    • Qualification
    • Training
    • Integration
  • Latest
  • Latest menu

    • News
    • Blog
    • Events
    • Videos
  • Downloads
  • Downloads menu

    • Brochures
    • Webinars
    • White Papers
    • Case Studies
    • Product briefs
    • Technical notes
    • Software licensing
  • Company
  • Company menu

    • About Rapita
    • Careers
    • Customers
    • Distributors
    • Industries
    • Locations
    • Partners
    • Research projects
    • Contact
  • Discover
    • Multicore Timing Analysis
    • Embedded Software Testing Tools
    • Worst Case Execution Time
    • WCET Tools
    • Code coverage for Ada, C & C++
    • MC/DC Coverage
    • Verifying additional code for DO-178C
    • Timing analysis (WCET) & Code coverage for MATLAB® Simulink®
    • Data Coupling & Control Coupling
    • Aerospace Software Testing
    • DO-178C
    • Meeting DO-178C Objectives
    • AC 20-193 and AMC 20-193
    • Meeting A(M)C 20-193 Objectives
    • Certifying eVTOL
    • Certifying UAS

All materials © Rapita Systems Ltd. 2025 - All rights reserved | Privacy information | Trademark notice Subscribe to our newsletter